I worked for GenRad as a digital electronic design engineer. GenRad designed and manufactured large in-circuit automated board test systems. I developed interface and control boards for the 2750 and 228x test systems and developed diagnostic test code for the 228x systems.
I started working at GenRad as a coop student from Northeastern University. As a coop job, GenRad was a wonderful place to work. The company clearly viewed their involvement with coop as a recruiting tool and all of my coop assignments were learning opportunities. I designed microprocessor boards, phase lock loops and wrote system test code in C and C++. Upon graduation I was offered a position as a digital designer and was happy to accept.
I implemented a VME bus based interface card designed to allow a VME based computer to interact with the 2750 test system’s proprietary control bus. The board was U9 sized and allowed both direct read and write operations between the two busses and provided a shared DRAM array (16 MBytes which felt huge at the time) accessible to both busses. Designing this board gave me a much better appreciation for the issues around the design of asynchronous arbiters.
It was my first ‘real’ board design with the final version of the board fabricated as a six layer printed circuit board (coop projects has all been wire-wrap or circuitry over ground plane for analog or high speed ECL stuff). Debugging the board design involved working with a member of the software team to create a Unix driver and user mode test harness to exercise the design.
For some time after this first design I worked on backplane characterizations, smaller product redesign and triage work and such.
When a high speed upgrade was proposed for the 228x test system (10 MHz test rate…fast at the time) I was assigned the test sequencer design. The test sequencer looks like a microprogrammable controller implemented in MSI and PALs with a PLL generated clock (from a separate clock generator board) that could run from 10 MHz down to essentially DC. Each time the clock ticked another sequencer instruction would be executed and all of the test subsystem control bits associated with that address would be sent to the ‘pin’ cards that carried out the test actions.
The sequencer was a very interesting piece of work. The basic implementation looked like the internals of a bit slice instruction sequencer. There was a small call stack (16 levels) and a full set of flow control instructions. Flow control could also be conditioned on test system results from the pin cards. The clock distribution scheme for this rather large card used low skew ECL-10K parts with ECL to TTL translators at the far end.
In the end, GenRad was struggling financially. After a downsizing of the engineering team I wound up working for a time supporting the IT team. My interests have long been in development engineering and so finally I left GenRad and started work as a firmware developer at Howtek.